Products — FPGA IP cores
Spacecraft data buses, in qualifiable VHDL
A line of IP cores for spacecraft avionics buses, developed to ECSS-E-ST-20-40C and ECSS-Q-ST-60-03C at
criticality category B and to the ESA IP core technical requirements. Each IP core comes with its full data package:
requirements, architecture, interfaces, verification plan and results, data sheet.
BES1553
MIL-STD-1553B · ECSS-E-ST-50-13Cv1.0 available
Connects a host (a processor, or user logic in the same FPGA) to a MIL-STD-1553B data bus. The services of the
space protocol and all their timing are implemented in hardware: no real-time software on the bus side.
- Terminal role selected at synthesis: Bus Controller, Remote Terminal or Bus Monitor
- Dual-redundant bus (channels A and B) or single channel
- Bus Controller: direct transfers, mode commands, Data Block Transfer, Data Wrap Around, Time Distribution
and Synchronization, Communication Frames and schedule table (Accurate Message Transfer)
- Remote Terminal: 30 transmit and 30 receive subaddresses, double-buffered, broadcast, illegal-command
detection
- Bus Monitor: both channels, nine error flags, timestamps, filter, start and stop triggers
- Built-in On-Board Time Master (BESOBT): CCSDS CUC format, Time Tick every 1 to 15 s, PPS steering
- AMBA AXI4-Lite, APB or native register port host interfaces
- Single-event upset protection of every state machine: detection, recovery and report
- Technology-independent VHDL-93, one clock domain (32 MHz by default)
298tests, three configurations
99.9 %statement coverage
84/84state machine states reached
15 %timing margin met on FPGA
Synthesized netlist checked against two independent implementations, state
machine protection verified by fault injection, system scenarios (one BC, three RTs and one BM on one bus).
BESSPW
SpaceWire · ECSS-E-ST-50-12C Rev.1in development
Multi-port SpaceWire node: links, protocols and time distribution in hardware, packet data exchanged by DMA
with the host memory.
- Number of ports set at synthesis, designed for 400 Mb/s per port and direction
- RMAP as target and as initiator (ECSS-E-ST-50-52C)
- CCSDS packet transfer, CPTP (ECSS-E-ST-50-53C), protocol identification (ECSS-E-ST-50-51C)
- Time-codes and distributed interrupts, BESOBT on-board time
- Recording of the traffic of its own links and, through an external tap, of links between other units:
analysis and debugging of SpaceWire networks
- Register interface (AXI4-Lite or APB), DMA interface, interrupts
303requirements traced to the standards
400Mb/s per port (target)
Requirements and architecture defined; RTL design and verification in progress,
with the method and tooling of BES1553.
BESOBT v1.0
On-Board Time Master: CCSDS CUC counter (32-bit coarse, 24-bit fine time), Time Tick every 1 to 15 s,
rate adjustment, proportional-integral steering onto an external PPS, scheduled loads.
BESHOST v1.0-rc1
AMBA AXI4-Lite and APB adapters to the register port of the BES IP cores, and interrupt controller.
Shared by the whole line.
Target: a SpaceWire / MIL-STD-1553 ↔ Ethernet gateway, to drive existing 1553 and
SpaceWire equipment from an Ethernet-native on-board computer. Fully open-source toolchain (GHDL, cocotb, Yosys,
nextpnr), prototyping on the European GateMate FPGA. Data sheets on request.
BES